The present invention relates to a method for fabricating a semiconductor device, and more particularly, to a method for forming a transistor in a semiconductor device.
As semiconductor devices become highly integrated, a size of the semiconductor devices become decreased. Thus, there are limitations such as increasing of a junction leakage and an electric field and a short channel effect as a doping concentration to a substrate increases.
A fin electric field effect transistor (hereinafter, a fin transistor) has been suggested to overcome the above limitations. In the fin transistor, a sufficient amount of current may be obtained by enlarging the channel region by having it at least promptly protrude vertically from the substrate.
A method for fabricating a typical fin transistor structure will be described hereinafter referring to FIGS. 1 to 2C.
FIG. 1 illustrates a perspective view of the typical fin transistor structure. A substrate 11 includes a vertically protruding fin active region 11A and an isolation layer 12. The fin active region 11A is divided into an upper portion and a lower portion with respect to a surface of the isolation layer 12. The isolation layer 12 encloses sidewalls of the lower portion of the fin active region 11A. A gate electrode 13 crossing the fin active region 11A is formed over the substrate 11 having the isolation layer 12. As shown, the gate electrode 13 covers a portion of the upper portion of the fin active region 11A and a channel region is formed along the portion of the fin active region 11A covered with the gate electrode 13. Since three sides of the fin active region 11A covered with the gate electrode 13 may be used as a channel, the channel region can be increased. Reference symbols S and D represent a source region and a drain region, respectively.
FIGS. 2A to 2C illustrate cross-sectional views of a method for fabricating the typical fin transistor along the line A-A′ shown in FIG. 1. The same or like reference numerals in FIGS. 2A to 2C corresponding to FIG. 1 will be used.
Referring to FIG. 2A, a trench t is formed on an isolation target region in the substrate 11 in order to form a vertically protruding fin active region 11A. Then, the isolation layer 12 is formed in the trench t.
Referring to FIG. 2B, the isolation layer 12 is selectively etched to leave a given thickness by a dry etching or a wet etching process in order to expose the upper portion of the fin active region 11A. A reference numeral 12A represents the isolation layer 12 after performing the dry etching or the wet etching process.
Referring to FIG. 2C, after forming a gate insulation layer (not shown) along the portion of an exposed upper portion of the fin active region 11A, a conductive layer for a gate electrode is formed over the etched isolation layer 12A and the gate insulation layer. A gate electrode 13 that crosses the fin active region 11A and also covers the fin active region 11A is formed by patterning the conductive layer. Subsequently, a channel region c is formed along the portion of the surface of the fin active region 11A that is covered by the gate electrode 13. Thus, a sufficient amount of current may be obtained due to the channel region enlarged by the method described hereinbefore. However, as semiconductor devices become more highly integrated, there is a need to further enlarge a surface area of the channel region of the semiconductor devices.